In semiconductor memories, Read data, which is sensed and restored on the bitlines of a memory array, are typically transported to output pins or pads of the semiconductor memory via long data bus lines. The bus lines are connected to the bitlines through column access devices. These column access devices are usually n-channel pass transistors. Reduction of the delay in propagating read data from the bitline to the data bus is limited by the low drive capabilities of the column access device and the heavy capacitive load of the data bus trace. The column access device size and drive is constrained by several factors. The first is the need to prevent an excessive capacitive burden on the bitlines especially in the case of DRAMs where bitline capacitance is a constraint on the speed of sensing. The second, is the need to eliminate the chance of the sense amplifier being flipped due to an incorrect state when attempting to read data whose value is a complementary value to the initial state of the data bus prior to the enabling of the column access device.
To avoid excessive read latency due to slow voltage transitions on the data bus lines, it is typical for the data bus lines to be grouped into complementary pairs that are connected to respective complementary bitline pairs through respective column access devices. The voltage differential on the data bus pair due to data readout from the associated bitline pair is amplified by a differential amplifier (the data bus sense amplifier). In a memory with a synchronous interface the amplified read data is typically latched by a single ended input D-type flip-flop before it is transmitted to the output pin or pad as shown in FIG. 1(a). A drawback of this approach is that the sequential nature of the read process and the serial timing required by the traditional approach of using a differential amplifier interposed between a data bus pair DB and DB and a single ended input flip-flop adds unnecessary delay to read operations which can limit the cycle time. It is thus desirable to speed up the memory Read operation.